Monolithic integration has emerged to reduce cost and to improve transient performance of power converters including dc-dc converters. There have been feasibility studies, and calculations suggested that power density exceeding 1000 W/cm2 is feasible at efficiency above 80%. State-of-the-art power density, however, currently has not exceeded 20 W/cm2 at output power above 10 W. To increase the power density of an integrated dc-dc converter requires micro-fabrication of inductors and capacitors referred to as power passives on the processor chips instead of requiring off-chip inductors and capacitors. There are presently no known practical fabrication techniques for fabricating power passives with high energy density. Other requirements for improving the power density and transient performance of dc-dc converters are design optimization, circuit topologies, magnetic geometries, materials, packaging, and thermal management, if a significant improvement above the state of the art 10 W power level and 20 W/cm2 power density are to be realized. Furthermore, many applications of power converters require high current capacity (˜10 A) and high inductance (˜μH).
Micro-electro-mechanical systems (MEMS) technology is an emerging technology which leverages IC technology to make micro-scale devices and systems. Numerous MEMS inductor designs have been reported where the main effort was focused on reducing losses. Several power loss mechanisms in an inductor exist, including: copper loss due to the resistance of the copper wire windings; core loss due to hysteresis and eddy currents in the core; eddy current loss due to a non-insulator substrate; dielectric loss; and electromagnetic radiation. Copper loss can be reduced by using thick copper layers which are normally obtained by employing deep polymer trenches. Core loss can be reduced by using lamination techniques. Substrate eddy current loss has been reduced through various methods, such as undercutting substrate, lifting the inductor structure above the substrate, or bending it out of plane. Dielectric loss and EM radiation are generally negligible.
There are many issues to be solved with MEMS inductors. Silicon-based micro-inductors offer the advantage of integratability with active electronics, but substrate loss and parasitic capacitances limit the achievable Q. Mechanical robustness is a concern if the substrate is removed or the microstructure is hung above or out of the substrate, where packaging difficulties must be addressed. Fabrication using microwave plasma ashing to remove thick polymer (>150 μm) such as SU-8 is time-consuming and can have undesired side effects especially on CMOS substrates. Because of the skin effect, increasing the copper line width may not yield low ac resistance at high frequency. Low inductance and low current handling because of winding resistance and core saturation should be improved upon and problems of thermal dissipation should be addressed.
Besides output capacitors, power supplies also need capacitors with large capacitance. To reduce the capacitor size, high capacitance-density capacitors are needed. High capacitance-density capacitors have been reported using V-grooves, multilayer stacks or high-k dielectrics. Ferroelectric dielectric materials (e.g., BST, PZT) have very high dielectric constants in the order of thousands. However they need high-temperature (>600° C.) annealing in oxygen and their dielectric constants decrease with DC bias and frequency. Paraelectric dielectrics (e.g., AlN, Ta2O5) are much more stable and can be deposited at low temperature, but their dielectric constants are only up to 50. A MIM capacitor with 1.7 μF/cm2 capacitance density was demonstrated using Nb2O5. Creating nanometer-scale shallow trenches on silicon can greatly increase the capacitance density and 3.13 μF/cm2 has been reported. The capacitance density achieved so far using multiple Ta2O5 layers is only about 440 nF/cm2 since the number of dielectric layers was limited to two. Using multilayer stacks to obtain high capacitance density seems to be an obvious approach to increase capacitance density, but the state of the art method to electrically connecting tens of layers separately requires an equal number of photolithography steps. This approach to is very complicated and very expensive.
A cross sectional view of a portion of a state-of-art integrated power converter 50 is shown in FIG. 1 where the converter 50 includes a CMOS layer 58. The power converter chip has integrated inductors, but no integrated large value capacitors. More specifically, the copper forming inductors 52 are imbedded in a insulating material 54 disposed on top of a silicon substrate 56 and the output capacitors are not integrated. The converter of FIG. 1 achieves only a moderate power density. Hence, the goal of an integrated dc-dc converter with improved power density remains unfulfilled. To achieve this goal a new method of fabricating power passives and corresponding structures is needed to achieve CMOS compatibility, high energy density and a small footprint.